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AD7476/ad7477 a rev. prf 08/99 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 1998 1msps, 10- / 12-bit adcs in 6 lead sot-23 preliminary technical data preliminary technical data functional block diagram features fast throughput rate: 1msps specified for v dd of 2.35 v to 5.25 v low power: 3.6mw typ at 1msps with 3v supplies 15mw typ at 1msps with 5v supplies wide input bandwidth: 70db snr at 200khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi/qspi/ m m m m m wire/dsp compatible standby mode: 1 a max 6-lead sot-23 package general description the AD7476/ad7477 are 12-bit and 10-bit, high speed, low power, successive-approximation adcs respectively. the parts operate from a single 2.35 v to 5.25 v power supply and feature throughput rates up to 1msps. the parts contain a low-noise, wide bandwidth track/hold am- plifier which can handle input frequencies in excess of 1mhz. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the devices to interface with microprocessors or dsps. the input signal is sampled on the falling edge of cs and the conversion is also initiated at this point. there are no pipelined delays associated with the part. the AD7476/ad7477 use advanced design techniques to achieve very low power dissipation at high throughput rates. the reference for the part is taken internally from v dd. the analog input range for the part is 0 to v dd . the con- version rate is determined by the sclk. product highlights 1. first 10-/12-bit adcs in a sot-23 package. 2. high throughput with low power consumption 3. flexible power/serial clock speed management the conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. this allows the average power cunsumption to be reduced when a powerdown mode is used while not converting. the part also features a shut- down mode to maximize power efficiency at lower throughput rates. power consumption is 1 m a max when in shutdown. 4. no pipeline delay the part features a standard successive-approximation adc with accurate control of the sampling instant via a cs input and once off conversion control. t/h vin AD7476/ad7477 vdd 10-/12-bit successive approximation adc sclk control logic sdata cs gnd
C2C rev. prf AD7476Cspecifications 1 ( v dd = +2.35 v to +5.25 v, a grade: f sclk = 20mhz, f sample = 1msps unless otherwise noted; b grade: f sclk = 11mhz, f sample = 600ksps unless otherwise noted; t a = t min to t max , unless otherwise noted.) preliminary technical data parameter a version 1 b version 1 units test conditions/comments dynamic performance f in = 200khz sine wave a grade: v dd = (2.7v to 5.25v) 4 signal to noise + distortion (sinad) 70 70 db min signal to noise ratio (snr) 70 70 db min total harmonic distortion (thd) C76 -76 db max peak harmonic or spurious noise (sfdr) C76 -76 db max intermodulation distortion (imd) second order terms C78 -78 db typ third order terms C78 -78 db typ aperture delay 10 10 ns max aperture jitter 10 10 ps typ full power bandwidth 5 5 mhz typ @ 3 db dc accuracy b grade, v dd = (2.35v to 3.6v) 5 . resolution 12 12 bits integral nonlinearity 1.5 lsb max 1.5 1 lsb typ differential nonlinearity 0.9 lsb max guaranteed no missed codes to 12 bits. 0.9 lsb typ offset error 3 lsb max 3 lsb typ gain error 3 lsb max 3 lsb typ analog input input voltage ranges 0 to v dd 0 to v dd volts dc leakage current 1 1 a max input capacitance 20 20 pf typ logic inputs input high voltage, v inh 2.8 2.8 v min v dd = 5v 2.4 2.4 v min v dd = 3v input low voltage, v inl 0.4 0.4 v max input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 2 10 10 pf max logic outputs output high voltage, v oh v dd -0.2 v dd -0.2 v min i source = 200 a; v dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 0.4 v max i sink =200 a floating-state leakage current 10 10 a max floating-state output capacitance 2 10 10 pf max output coding straight (natural) binary conversion rate conversion time 0.8 1.45 s max 16 sclk cycles track/hold acquisition time 400 400 ns max throughput rate 1000 600 ksps max conversion time + quiet time.
C3C preliminary technical data AD7476Cspecifications 1 rev. prf ( v dd = +2.35 v to +5.25 v, a grade: f sclk = 20mhz, f sample = 1msps unless otherwise noted; b grade: f sclk = 11mhz, f sample = 600ksps unless otherwise noted; t a = t min to t max , unless otherwise noted.) parameter a version 1 b version 1 units test conditions/comments power requirements v dd +2.35/+5.25 +2.35/+5.25 v min/max i dd 4 digital i/ps = 0v or v dd . normal mode(static) 2.1 2.1 ma typ v dd = 4.75v to 5.25v. sclk on or off. 1 1 ma typ v dd = 2.35v to 3.6v. sclk on or off. normal mode (operational) 4 3 ma max v dd = 4.75v to 5.25v.f sample =f sample max 6 2 1.7 ma max v dd = 2.35v to 3.6v.f sample = f sample max 6 full power-down mode 1 1 a max sclk on or off. power dissipation 3 normal mode (operational) 20 15 mw max v dd = 5v. f sample = f sample max 6 6 5.1 mw max v dd = 3v. f sample = f sample max 6 full power-down 5 5 w max v dd = 5 v. 3 3 w max v dd = 3 v. notes 1 temperature ranges as follows: a, b versions: C40c to +85c. 2 sample tested @ +25c to ensure compliance. 3 see power versus throughput rate section. 4 a grade spec applies as a typical figure when v dd = 2.35v. 5 b grade spec applies as a typical figure when v dd = 5.25v. 6 a grade: f sample max = 1msps; b grade: f sample max = 600ksps. specifications subject to change without notice.
preliminary technical data ad7477Cspecifications 1 ( v dd = +2.7 v to +5.25 v, f sclk = 20mhz unless otherwise noted; t a = t min to t max , unless otherwise noted.) rev. prf parameter ad7477 1 units test conditions/comments dynamic performance signal to noise + distortion (sinad) 61 db min f in = 200khz sine wave, f sample = 1msps signal to noise ratio (snr) 61 db min f in = 200khz sine wave, f sample = 1msps total harmonic distortion (thd) -76 db max f in = 200khz sine wave, f sample = 1msps peak harmonic or spurious noise (sfdr) -76 db max f in = 200khz sine wave, f sample = 1msps intermodulation distortion (imd) second order terms -67 db typ third order terms -67 db typ aperture delay 10 ns max aperture jitter 10 ps typ full power bandwidth 5 mhz typ @ 3 db dc accuracy resolution 10 bits integral nonlinearity 1 lsb max differential nonlinearity 0.9 lsb max guaranteed no missed codes to 10 bits. offset error 1 lsb max gain error 1 lsb max analog input input voltage ranges 0 to v dd volts dc leakage current 1 a max input capacitance 20 pf typ logic inputs input high voltage, v inh 2.8 v min v dd = 5v 2.4 v min v dd = 3v input low voltage, v inl 0.4 v max input current, i in 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 2 10 pf max logic outputs output high voltage, v oh v dd -0.2 v min i source = 200 a; v dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 v max i sink =200a floating-state leakage current 10 a max floating-state output capacitance 2 10 pf max output coding straight (natural) binary conversion rate conversion time 800 ns max 16 sclk cycles with sclk at 20mhz track/hold acquisition time 400 ns max throughput rate 1 msps max conversion time + quiet time. power requirements v dd +2.7/+5.25 v min/max i dd 4 digital i/ps = 0v or v dd . normal mode(static) 2.1 ma typ v dd = 4.75v to 5.25v. sclk on or off. 1 ma typ v dd = 2.7v to 3.6v. sclk on or off. normal mode (operational) 4 ma max v dd = 4.75v to 5.25v. f sample = 1msps 2 ma max v dd = 2.7v to 3.6v. f sample = 1msps full power-down mode 1 a max sclk on or off. power dissipation 3 normal mode (operational) 20 mw max v dd = 5v. f sample = 1msps 6 mw max v dd = 3v. f sample = 1msps full power-down 5 w max v dd = 5 v. notes 1 temperature ranges as follows: a, b versions: C40c to +85c. 2 sample tested @ +25c to ensure compliance. 3 see power versus throughput rate section. specifications subject to change without notice.
AD7476/ad7477 C5C rev. prf preliminary technical data preliminary technical data limit at t min , t max parameter AD7476/ad7477 units description a version b version f sclk 2 10 10 khz min 20 11 mhz max t convert 16* t sclk 16* t sclk t sclk = 1/f sclk ns max f sclk = mhz t quiet 100 100 ns min minimum quiet time required between conversions t 2 10 10 ns min cs to sclk setup time t 3 3 tbd tbd ns max delay from cs until sdata 3-state disabled t 4 3 10 10 ns max data access time after sclk falling edge t 5 tbd tbd ns min data setup time prior to sclk falling edge t 6 0.4t sclk 0.4t sclk ns min sclk high pulse width t 7 0.4t sclk 0.4t sclk ns min sclk low pulse width t 8 5 5 ns min sclk to data valid hold time t 9 4 25 25 ns max sclk falling edge to sdata high impedance t 10 11 m s typ power up time from full power-down timing specifications 1 notes 1 sample tested at +25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 volts. see figure 2. 2 mark/space ratio for the sclk input is 40/60 to 60/40. 3 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.0 v. 4 t 9 is derived form the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 9 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. specifications subject to change without notice. ( v dd = +2.35 v to +5.25 v; t a = t min to t max , unless otherwise noted.) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7476/ad7477 feature proprietary esd protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide linearity package model range error (lsb) 1 option 2 branding AD7476art -40c to +85c 1.5 typ rt-6 cea AD7476brt -40c to +85c 1.5 max rt-6 c e b ad7477art -40c to +85c 1 max rt-6 c f a notes 2 rt = sot-23. absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd C0.3 v to 7 v analog input voltage to gnd C0.3 v to v dd + 0.3 v digital input voltage to gnd C0.3 v to 7 v digital output voltage to gnd C0.3 v to v dd + 0.3 v input current to any pin except supplies 2 10 ma operating temperature range commercial (a, b version) C40c to +85c storage temperature range C65c to +150c junction temperature +150c sot-23 package, power dissipation 450 mw q ja thermal impedance 229.6 c/w (sot23) q jc thermal impedance 91.99c/w (sot23) figure 1. load circuit for digital output timing specifications lead temperature, soldering vapor phase (60 secs) +215c infared (15 secs) +220c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. +1.6v i ol 200a 200a i oh to output pin c l 50pf
AD7476/ad7477 C6C rev. prf preliminary technical data preliminary technical data pin function description pin pin no. mnemonic function 6 cs chip select. active low logic input. this input provides the dual function of initiating con- versions on the AD7476/ad7477 and also frames the serial data transfer. 1v dd power supply input. the v dd range for the AD7476/ad7477 is from +2.35v to +5.25v. 2 g n d analog ground. ground reference point for all circuitry on the AD7476/ad7477. all analog input signals and any external reference signal should be referred to this gnd voltage. 3 vin analog input. single-ended analog input channel. the input range is 0 to v dd . 5 sdata d ata out. logic output. the conversion result from the AD7476/ad7477 is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream consists of four leading zeros followed by the 12 bits of conversion data which is provided msb first. 4 sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the AD7476/ad7477's conversion pro- cess. AD7476/ad7477 pinconfiguration sot-23 AD7476/77 top view 1 2 3 4 5 6 cs sdata sclk v dd gnd v in (not to scale)
AD7476/ad7477 C7C rev. prf preliminary technical data preliminary technical data terminology integral nonlinearity this is the maximum deviation from a straight line pass- ing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e agnd + 1lsb gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., v ref C 1 lsb) after the offset error has been adjusted out. track/hold acquisition time the track/hold amplifier returns into track mode and the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 0.5 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distor- tion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db and for a 10- bit converter this is 62db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the AD7476/ ad7477, it is defined as: where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms in- clude (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the AD7476/ad7477 are tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a fre- quency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. thd (db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1
AD7476/ad7477 C8C rev. prf preliminary technical data preliminary technical data modes of operation the mode of operation of the AD7476/ad7477 is se- lected by controlling the (logic) state of the cs signal during a conversion . there are two possible modes of operation, normal mode and power-down mode. the point at which cs is pulled high after the conversion has been initiated will determine whether the AD7476/ ad7477 will enter power-down mode or not. similarly, if already in power-down then cs can control whether the device will return to normal operation or remain in power-down. these modes of operation are designed to provide flexible power management options. these op- tions can be chosen to optimize the power dissipation/ throughput rate ratio for differing application require- ments. normal mode this mode is intended for fastest throughput rate perfor- mance as the user does not have to worry about any power-up times with the AD7476/ad7477 remaining fully-powered all the time. figure 2 shows the general diagram of the operation of the AD7476/ad7477 in this mode. the conversion is iniated on the falling edge of cs as described in the serial interface section. to ensure the part remains fully powered up at all times cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10th sclk falling edge but before the 16th sclk falling edge the part will remain powered up but the conversion will be terminated and sdata will go back into tri-state. sixteen serial clock cycles are required to complete the conversion and access the complete con- version result. cs may idle high until the next conversion or may idle low until sometime prior to the next conver- sion, (effectively idling cs low). once a data transfer is complete (sdata has returned to tri-state), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again. figure 2. normal mode operation power-down mode this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and then the adc is powered down for a relatively long duration between these bursts of several conversions. when the AD7476/ad7477 is in power down, all analog circuitry is powered down. to enter power-down, the conversion process must be interrupted by bringing cs high anywhere after the second falling edge of sclk and before the tenth falling edge of sclk as shown in figure 3. once cs has been brought high in this window of sclks, then the part will enter power down and the conversion that was intiated by the falling edge of cs will be terminated and sdata will go back into tri-state. if cs is brought high before the second sclk falling edge, then the part will remain in normal mode and will not power-down. this will avoid accidental powerdown due to glitches on the cs line. in order to exit this mode of operation and power the AD7476/ad7477 up again, a dummy conversion is per- formed. on the falling edge of cs the device will begin to power up, and will continue to power up as long as cs is held low until after the falling edge of the tenth sclk. the device will be fully powered up once 16 sclks have elapsed and valid data will result from the next conversion as shown in figure 4. if cs is brought high before the tenth falling edge of sclk, then the AD7476/ad7477 will go back into power down again. this avoids acciden- tal power up due to glitches on the cs line or an inadvert- ent burst of 8 sclk cycles while cs low. so although the device may begin to power up on the falling edge of cs , it will power down again on the rising edge of cs as long as it occurs before the tenth sclk falling edge. sclk tri-state cs sdata 1 16 10 2 figure 3. entering power down mode sclk 4 leading zeroes + conversion result cs sdata 1 16 10
AD7476/ad7477 C9C rev. prf preliminary technical data preliminary technical data sclk cs sdata invalid data valid data 1 10 16 16 1 the part begins to power up the part is fully powered up figure 4. exiting power down mode serial interface figure 5 and figure 6 show the detailed timing diagram for serial interfacing to the AD7476 and the ad7477 re- spectively. the serial clock provides the conversion clock and also controls the transfer of information from the AD7476/ad7477 during conversion. cs initiates the data transfer and conversion process. the falling edge of cs puts the track and hold into hold mode, takes the bus out of tristate and the analog input is sampled at this point. the conversion is also initiated at this point and will require 16 sclk cycles to complete. once 13 sclk falling edges have elapsed, then the track and hold will go back into track on the next sclk rising edge. on the 16th sclk falling edge the sdata line will go back into tristate . if the rising edge of cs occurs before 16 sclks have elapsed then the conversion will be terminated and the sdata line will go back into tri- state, otherwise sdata returns to tri-state on the 16th sclk falling edge as shown in figure 5 and figure 6. sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476/ ad7477. cs going low provides the first leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges beginning with the 2nd leading zero, thus the first falling clock edge on the serial clock has the second leading zero provided. the final bit in the data transfer is valid on the sixteenth falling edge, having being clocked out on the previous (15th) falling edge. in applications with a slower sclk, it may be possible to read in data on each sclk rising edge, i.e. the first rising edge of sclk after the cs falling edge would provide the first leading zero and the 15th risng sclk edge would provide db0. figure 5. AD7476 serial interface timing diagram cs sclk 1 56 15 sdata 4 leading zero's 3-state t 4 2 34 16 t 5 t 3 t quiet t convert t 2 3-state db11 db10 db9 db0 t 6 t 9 t 8 14
AD7476/ad7477 C10C rev. prf preliminary technical data preliminary technical data figure 6. ad7477 serial interface timing diagram cs sclk 1 56 15 sdata 4 leading zero's 3-state t 4 2 34 16 t 5 t 3 t quiet t convert t 2 3-state db9 db8 db7 t 6 t 9 t 8 14 2 trailing zero's zero zero
AD7476/ad7477 C11C rev. prf preliminary technical data preliminary technical data 6-lead sot23 (rt-6) outline dimensions dimensions shown in inches and (mm). 0.122 (3.10) 0.106 (2.70) pin 1 0.118 (3.00) 0.098 (2.50) 0.075 (1.90) bsc 0.037 (0.95) bsc 1 3 4 5 6 2 0.071 (1.80) 0.059 (1.50) 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 0 0.020 (0.50) 0.010 (0.25) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90)

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